数字设计和计算机体系结构 英文版 第2版 ARM版PDF电子书下载

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Chapter 1 From Zero to One 3

1.1 The Game Plan 3

1.2 The Art of Managing Complexity 4

1.2.1 Abstraction 4

1.2.2 Discipline 5

1.2.3 The Three-Y’s 6

1.3 The Digital Abstraction 7

1.4 Number Systems 9

1.4.1 Decimal Numbers 9

1.4.2 Binary Numbers 9

1.4.3 Hexadecimal Numbers 11

1.4.4 Bytes，Nibbles，and All That Jazz 13

1.4.5 Binary Addition 14

1.4.6 Signed Binary Numbers 15

1.5 Logic Gates 19

1.5.1 NOT Gate 20

1.5.2 Buffer 20

1.5.3 AND Gate 20

1.5.4 OR Gate 21

1.5.5 Other Two-Input Gates 21

1.5.6 Multiple-Input Gates 21

1.6 Beneath the Digital Abstraction 22

1.6.1 Supply Voltage 22

1.6.2 Logic Levels 22

1.6.3 Noise Margins 23

1.6.4 DC Transfer Characteristics 24

1.6.5 The Static Discipline 24

1.7 CMOS Transistors 26

1.7.1 Semiconductors 27

1.7.2 Diodes 27

1.7.3 Capacitors 28

1.7.4 nMOS and pMOS Transistors 28

1.7.5 CMOS NOT Gate 31

1.7.6 Other CMOS Logic Gates 31

1.7.7 Transmission Gates 33

1.7.8 Pseudo-nMOS Logic 33

1.8 Power Consumption 34

1.9 Summary and a Look Ahead 35

Exercises 37

Interview Questions 52

Chapter 2 Combinational Logic Design 55

2.1 Introduction 55

2.2 Boolean Equations 58

2.2.1 Terminology 58

2.2.2 Sum-of-Products Form 58

2.2.3 Product-of-Sums Form 60

2.3 Boolean Algebra 60

2.3.1 Axioms 61

2.3.2 Theorems o f One Variable 61

2.3.3 Theorems o f Several Variables 62

2.3.4 The Truth Behind It All 64

2.3.5 Simplifying Equations 65

2.4 From Logic to Gates 66

2.5 Multilevel Combinational Logic 69

2.5.1 Hardware Reduction 70

2.5.2 Bubble Pushing 71

2.6 X’s and Z’s，Oh My 73

2.6.1 Illegal Value： X 73

2.6.2 Floating Value： Z 74

2.7 Karnaugh Maps 75

2.7.1 Circular Thinking 76

2.7.2 Logic Minimization with K-Maps 77

2.7.3 Don’t Cares 81

2.7.4 The Big Picture 82

2.8 Combinational Building Blocks 83

2.8.1 Multiplexers 83

2.8.2 Decoders 86

2.9 Timing 88

2.9.1 Propagation and Contamination Delay 88

2.9.2 Glitches 92

2.10 Summary 95

Exercises 97

Interview Questions 106

Chapter 3 Sequential Logic Design 109

3.1 Introduction 109

3.2 Latches and Flip-Flops 109

3.2.1 SR Latch 111

3.2.2 D Latch 113

3.2.3 D FIip-Flop 114

3.2.4 Register 114

3.2.5 Enabled Flip-Flop 115

3.2.6 Resettable Flip-Flop 116

3.2.7 Transistor-Level Latch and Flip-Flop Designs 116

3.2.8 Putting It All Together 118

3.3 Synchronous Logic Design 119

3.3.1 Some Problematic Circuits 119

3.3.2 Synchronous Sequential Circuits 120

3.3.3 Synchronous and Asynchronous Circuits 122

3.4 Finite State Machines 123

3.4.1 FSM Design Example 123

3.4.2 State Encodings 129

3.4.3 Moore and Mealy Machines 132

3.4.4 Factoring State Machines 134

3.4.5 Deriving an FSM from a Schematic 137

3.4.6 FSM Review 140

3.5 Timing of Sequential Logic 141

3.5.1 The Dynamic Discipline 142

3.5.2 System Timing 142

3.5.3 Clock Skew 148

3.5.4 Metastability 151

3.5.5 Synchronizers 152

3.5.6 Derivation o f Resolution Time 154

3.6 Parallelism 157

3.7 Summary 161

Exercises 162

Interview Questions 171

Chapter 4 Hardware Description Languages 173

4.1 Introduction 173

4.1.1 Modules 173

4.1.2 Language Origins 174

4.1.3 Simulation and Synthesis 175

4.2 Combinational Logic 177

4.2.1 Bitwise Operators 177

4.2.2 Comments and White Space 180

4.2.3 Reduction Operators 180

4.2.4 Conditional Assignment 181

4.2.5 Internal Variables 182

4.2.6 Precedence 184

4.2.7 Numbers 185

4.2.8 Zs and Xs 186

4.2.9 Bit Swizzling 188

4.2.10 Delays 188

4.3 Structural Modeling 190

4.4 Sequential Logic 193

4.4.1 Registers 193

4.4.2 Resettable Registers 194

4.4.3 Enabled Registers 196

4.4.4 Multiple Registers 197

4.4.5 Latches 198

4.5 More Combinational Logic 198

4.5.1 Case Statements 201

4.5.2 I f Statements 202

4.5.3 Truth Tables with Don’t Cares 205

4.5.4 Blocking and Nonblocking Assignments 205

4.6 Finite State Machines 209

4.7 Data Types 213

4.7.1 System Verilog 214

4.7.2 VHDL 215

4.8 Parameterized Modules 217

4.9 Testbenches 220

4.10 Summary 224

Exercises 226

Interview Questions 237

Chapter 5 Digital Building Blocks 239

5.1 Introduction 239

5.2 Arithmetic Circuits 239

5.2.1 Addition 239

5.2.2 Subtraction 246

5.2.3 Comparators 246

5.2.4 AL U 248

5.2.5 Shifters and Rotators 251

5.2.6 Multiplication 252

5.2.7 Division 254

5.2.8 Further Reading 255

5.3 Number Systems 255

5.3.1 Fixed-Point Number Systems 255

5.3.2 Floating-Point Number Systems 256

5.4 Sequential Building Blocks 259

5.4.1 Counters 260

5.4.2 Shift Registers 261

5.5 Memory Arrays 264

5.5.1 Overview 264

5.5.2 Dynamic Random Access Memory （DRAM） 266

5.5.3 Static Random Access Memory （SRAM） 267

5.5.4 Area and Delay 267

5.5.5 Register Files 268

5.5.6 Read Only Memory 268

5.5.7 Logic Using Memory Arrays 270

5.5.8 Memory HDL 271

5.6 Logic Arrays 271

5.6.1 Programmable Logic Array 272

5.6.2 Field Programmable Gate Array 274

5.6.3 Array Implementations 279

5.7 Summary 281

Exercises 282

Interview Questions 293

Chapter 6 Architecture 295

6.1 Introduction 295

6.2 Assembly Language 296

6.2.1 Instructions 297

6.2.2 Operands： Registers，Memory，and Constants 298

6.3 Programming 303

6.3.1 Data-processing Instructions 303

6.3.2 Condition Flags 306

6.3.3 Branching 308

6.3.4 Conditional Statements 309

6.3.5 Getting Loopy 312

6.3.6 Memory 313

6.3.7 Function Calls 317

6.4 Machine Language 329

6.4.1 Data-processing Instructions 329

6.4.2 Memory Instructions 333

6.4.3 Branch Instructions 334

6.4.4 Addressing Modes 336

6.4.5 Interpreting Machine Language Code 336

6.4.6 The Power of the Stored Program 337

6.5 Lights，Camera，Action： Compiling，Assembling，and Loading 339

6.5.1 The Memory Map 339

6.5.2 Compilation 340

6.5.3 Assembling 342

6.5.4 Linking 343

6.5.5 Loading 344

6.6 Odds and Ends 345

6.6.1 Loading Literals 345

6.6.2 NOP 346

6.6.3 Exceptions 347

6.7 Evolution of ARM Architecture 350

6.7.1 Thumb Instruction Set 351

6.7.2 DSP Instructions 352

6.7.3 Floating-Point Instructions 357

6.7.4 Power-Saving and Security Instructions 358

6.7.5 SIMD Instructions 358

6.7.6 64-bit Architecture 360

6.8 Another Perspective： x86 Architecture 360

6.8.1 x86 Registers 362

6.8.2 x86 Operands 362

6.8.3 Status Flags 363

6.8.4 x86 Instructions 364

6.8.5 x86 Instruction Encoding 364

6.8.6 Other x86 Peculiarities 367

6.8.7 The Big Picture 368

6.9 Summary 368

Exercises 370

Interview Questions 383

Chapter 7 Microarchitecture 385

7.1 Introduction 385

7.1.1 Architectural State and Instruction Set 385

7.1.2 Design Process 386

7.1.3 Microarchitectures 388

7.2 Performance Analysis 389

7.3 Single-Cycle Processor 390

7.3.1 Single-Cycle Datapath 390

7.3.2 Single-Cycle Control 397

7.3.3 More Instructions 402

7.3.4 Performance Analysis 402

7.4 Multicycle Processor 406

7.4.1 Multicycle Datapath 407

7.4.2 Multicycle Control 413

7.4.3 Performance Analysis 421

7.5 Pipelined Processor 425

7.5.1 Pipelined Datapath 428

7.5.2 Pipelined Control 430

7.5.3 Hazards 431

7.5.4 Performance Analysis 441

7.6 HDL Representation 443

7.6.1 Single-Cycle Processor 444

7.6.2 Generic Building Blocks 449

7.6.3 Testbench 452

7.7 Advanced Microarchitecture 456

7.7.1 Deep Pipelines 457

7.7.2 Micro-Operations 458

7.7.3 Branch Prediction 459

7.7.4 Superscalar Processor 461

7.7.5 Out-of-Order Processor 463

7.7.6 Register Renaming 465

7.7.7 Multithreading 467

7.7.8 Multiprocessors 468

7.8 Real-World Perspective： Evolution of ARM Microarchitecture 470

7.9 Summary 476

Exercises 478

Interview Questions 484

Chapter 8 Memory Systems 487

8.1 Introduction 487

8.2 Memory System Performance Analysis 491

8.3 Caches 492

8.3.1 What Data is Held in the Cache？ 493

8.3.2 How is Data Found？ 494

8.3.3 What Data is Replaced？ 502

8.3.4 Advanced Cache Design 503

8.3.5 The Evolution o f ARM Caches 507

8.4 Virtual Memory 508

8.4.1 Address Translation 510

8.4.2 The Page Table 512

8.4.3 The Translation Lookaside Buffer 514

8.4.4 Memory Protection 515

8.4.5 Replacement Policies 516

8.4.6 Multilevel Page Tables 516

8.5 Summary 518

Epilogue 519

Exercises 520

Interview Questions 529

Chapter 9 I/O Systems 531

9.1 Introduction 531

Appendix A Digital System Implementation 533

A.1 Introduction 533

Appendix A is available as an online supplement 533

A.1 Introduction 533

A.2 74xx Logic 533

A.2.1 Logic Gates 533

A.2.2 Other Functions 533

A.3 Programmable Logic 533

A.3.1 PROMs 533

A.3.2 PLAs 533

A.3.3 FPGAs 533

A.4 Application-Specific Integrated Circuits 533

A.5 Data Sheets 533

A.6 Logic Families 533

A.7 Packaging and Assembly 533

A.8 Transmission Lines 533

A.8.1 Matched Termination 533

A.8.2 Open Termination 533

A.8.3 Short Termination 533

A.8.4 Mismatched Termination 533

A.8.5 When to Use Transmission Line Models 533

A.8.6 Proper Transmission Line Terminations 533

A.8.7 Derivation o f Z0 533

A.8.8 Derivation o f the Reflection Coefficient 533

A.8.9 Putting It All Together 533

A.9 Economics 533

Appendix B ARM Instructions 535

B.1 Data-Processing Instructions 535

B.1.1 Multiply Instructions 537

B.2 Memory Instructions 538

B.3 Branch Instructions 539

B.4 Miscellaneous Instructions 539

B.5 Condition Flags 540

Appendix C C Programming 541

C.1 Introduction 541

Appendix C is available as an online supplement 541

C.1 Introduction 541

C.2 Welcome to C 541

C.2.1 C Program Dissection 541

C.2.2 Running a C Program 541

C.3 Compilation 541

C.3.1 Comments 541

C.3.2 ？define 541

C.3.3 ？include 541

C.4 Variables 541

C.4.1 Primitive Data Types 541

C.4.2 Global and Local Variables 541

C.4.3 Initializing Variables 541

C.5 Operators 541

C.6 Function Calls 541

C.7 Control-Flow Statements 541

C.7.1 Conditional Statements 541

C.7.2 Loops 541

C.8 More Data Types 541

C.8.1 Pointers 541

C.8.2 Arrays 541

C.8.3 Characters 541

C.8.4 Strings 541

C.8.5 Structures 541

C.8.6 typedef 541

C.8.7 Dynamic Memory Allocation 541

C.8.8 Linked Lists 541

C.9 Standard Libraries 541

C.9.1 stdio 541

C.9.2 stdlib 541

C.9.3 math 541

C.9.4 string 541

C.10 Compiler and Command Line Options 541

C.10.1 Compiling Multiple C Source Files 541

C.10.2 Compiler Options 541

C.10.3 Command Line Arguments 541

C.11 Common Mistakes 541

Index 543

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